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| CAT24C44 256-Bit Serial Nonvolatile CMOS Static RAM FEATURES s Single 5V Supply s Infinite EEPROM to RAM Recall s CMOS and TTL Compatible I/O s Low CMOS Power Consumption: s JEDEC Standard Pinouts: -8-pin DIP -8-pin SOIC s 100,000 Program/Erase Cycles (EEPROM) s Auto Recall on Power-up s Commercial, Industrial and Automotive -Active: 3 mA Max. -Standby: 30 A Max. s Power Up/Down Protection s 10 Year Data Retention Temperature Ranges s "Green" Package Options Available DESCRIPTION The CAT24C44 Serial NVRAM is a 256-bit nonvolatile memory organized as 16 words x 16 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy transfer of data from RAM array to EEPROM (STORE) and from EEPROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5s. The CAT24C44 features unlimited RAM write operations either through external RAM writes or internal recalls from EEPROM. Internal false store protection circuitry prohibits STORE operations when VCC is less than 3.5V (typical) ensuring EEPROM data integrity. The CAT24C44 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (EEPROM) and has a data retention of 10 years. The device is available in JEDEC approved 8-pin plastic DIP and SOIC packages. PIN CONFIGURATION DIP Package (P, L, GL) CE SK DI DO 1 2 3 4 8 7 6 5 PIN FUNCTIONS Pin Name Function Serial Clock Serial Input Serial Data Output Chip Enable Recall Store +5V Ground SK DI DO CE RECALL STORE VCC VSS SOIC Package (S, V, GV) 1 2 3 4 8 7 6 5 VCC STORE RECALL VSS VCC CE STORE SK RECALL DI VSS DO (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1083, Rev. R CAT24C44 BLOCK DIAGRAM EEPROM ARRAY RECALL ROW DECODE STATIC RAM ARRAY 256-BIT STORE CONTROL LOGIC STORE RECALL CE DI SK INSTRUCTION REGISTER COLUMN DECODE DO VCC VSS INSTRUCTION DECODE 4-BIT COUNTER MODE SELECTION(1)(2) Mode Hardware Recall(3) Software Recall Hardware Store(3) Software Store X = Don't Care STORE 1 1 0 1 RECALL 0 1 1 1 Software Instruction NOP RCL NOP STO Write Enable Latch X X SET SET Previous Recall Latch X X TRUE TRUE POWER-UP TIMING(4) Symbol VCCSR tpur tpuw Parameter VCC Slew Rate Power-Up to Read Operations Power-Up to Write or Store Operation Min. 0.5 Max. 0.005 200 5 Units V/m s ms Note: (1) The store operation has priority over all the other operations. (2) The store operation is inhibited when VCC is below 3.5V. (3) NOP designates that the device is not currently executing an instruction. (4) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1083, Rev. R 2 (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(2) ............. -2.0 to +VCC +2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. 100,000 10 2000 100 *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Typ. Max. Units Cycles/Byte Years Volts mA D.C. OPERATING CHARACTERISTICS VCC = 5V 10%, unless otherwise specified. Limits Symbol ICCO ISB ILI ILO VIH VIL VOH VOL Parameter Current Consumption (Operating) Current Consumption (Standby) Input Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage 2 0 2.4 0.4 Min. Typ. Max. 3 30 2 10 VCC 0.8 Unit mA A A A V V V V IOH = -2mA IOL = 4.2mA Conditions Inputs = 5.5V, TA = 0C All Outputs Unloaded CE = VIL 0 VIN 5.5V 0 VOUT 5.5V CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O (1) Parameter Input/Output Capacitance Input Capacitance Max. 10 6 Unit pF pF Conditions VI/O = 0V VIN = 0V CIN(1) Note: (1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1083, Rev. R CAT24C44 A.C. CHARACTERISTICS VCC = 5V 10%, unless otherwise specified. Symbol FSK tSKH tSKL tDS tDH tPD tZ tCES tCEH tCDS Parameter SK Frequency SK Positive Pulse Width SK Negative Pulse Width Data Setup Time Data Hold Time SK Data Valid Time CE Disable Time CE Enable Setup Time CE Enable Hold Time CE De-Select Time 800 400 800 Min. DC 400 400 400 80 375 1 Max. 1 Units MHz ns ns ns ns ns s ns ns ns CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Input rise and fall times = 10ns Conditions A.C. CHARACTERISTICS, Store Cycle VCC = 5V 10%, unless otherwise specified. Limits Symbol tST tSTP tSTZ Parameter Store Time Store Pulse Width Store Disable Time 200 100 Min. Max. 10 Units ms ns ns Conditions CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V A.C. CHARACTERISTICS, Recall Cycle VCC = 5V 10%, unless otherwise specified. Symbol tRCC tRCP tRCZ tORC tARC Parameter Recall Cycle Time Recall Pulse Width Recall Disable Time Recall Enable Time Recall Data Access Time 10 1.5 Min. 2.5 500 500 Max. Units s ns ns ns s CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Conditions INSTRUCTION SET Format Instruction WRDS STO WRITE WREN RCL READ X = Don't care A = Address bit Start Bit 1 1 1 1 1 1 Address XXXX XXXX AAAA XXXX XXXX AAAA OP Code 000 001 011 100 101 11X Operation Reset Write Enable Latch (Disables, Writes and Stores) Store RAM Data in EEPROM Write Data into RAM Address AAAA Set Write Enable Latch (Enables, Writes and Stores) Recall EEPROM Data into RAM Read Data From RAM Address AAAA Doc. No. 1083, Rev. R 4 (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 from the device: If the CE pin is prematurely deselected while shifting in an instruction, that instruction will not be executed, and the shift register internal to the CAT24C44 will be cleared. If there are more than or less than 16 clocks during a memory data transfer, an improper data transfer will result. The SK clock is completely static allowing the user to stop the clock and restart it to resume shifting of data. Read Upon receiving a start bit, 4 address bits, and the 3-bit read command (clocked into the DI pin), the DO pin of the CAT24C44 will come out of the high impedance state and the 16 bits of data, located at the address specified in the instructions, will be clocked out of the device. When clocking data from the device, the first bit clocked out (DO) is timed from the falling edge of the 8th clock, all succeeding bits (D1-D15) are timed from the rising edge of the clock. Write After receiving a start bit, 4 address bits, and the 3-bit WRITE command, the 16-bit word is clocked into the device for storage into the RAM memory location specified. The CE pin must remain high during the entire write operation. DEVICE OPERATION The CAT24C44 is intended for use with standard microprocessors. The CAT24C44 is organized as 16 registers by 16 bits. Seven 8-bit instructions control the device's operating modes, the RAM reading and writing, and the EEPROM storing and recalling. It is also possible to control the EEPROM store and recall functions in hardware with the STORE and RECALL pins. The CAT24C44 operates on a single 5V supply and will generate, on chip, the high voltage required during a RAM to EEPROM storing operation. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin remains in a high impedance state except when outputting data from the device. The CE (Chip Enable) pin must remain high during the entire data transfer. The format for all instructions sent to the CAT24C44 is a logical `1' start bit, 4 address bits (data read or write operations) or 4 "Don't Care" bits (device mode operations), and a 3-bit op code (see Instruction Set). For data write operations, the 8-bit instruction is followed by 16 bits of data. For data read instructions, DO will come out of the high impedance state and enable 16 bits of data to be clocked from the device. The 8th bit of the read instruction is a "Don't Care" bit. This is to eliminate any bus contention that would occur in applications where the DI and DO pins are tied together to form a common DI/DO line. A word of caution while clocking data to and Figure 1. RAM Read Cycle Timing CE 1 SK 2 3 4 5 6 7 8 9 10 11 12 22 23 24 (1) (8) DI 1 A A A A X 1 1 DO HIGH-Z D0 D1 D2 D3 D14 D15 D0 Figure 2. RAM Write Cycle Timing CE 1 SK 2 3 4 5 6 7 8 9 10 11 12 22 23 24 DI 1 A A A A 1 0 1 D0 D1 D2 D3 D13 D14 D15 Note: (1) Bit 8 of READ instruction is "Don't Care". (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1083, Rev. R CAT24C44 WREN/WRDS The CAT24C44 powers up in the program disable state (the "write enable latch" is reset). Any programming after power-up or after a WRDS (RAM write/EEPROM store disable) instruction must first be preceded by the WREN (RAM write/EEPROM store enable) instruction. Once writing/storing is enabled, it will remain enabled until power to the device is removed, the WRDS instruction is sent, or an EEPROM store has been executed (STO). The WRDS (write/store disable) can be used to disable all CAT24C44 programming functions, and will prevent any accidental writing to the RAM, or storing to the EEPROM. Data can be read normally from the CAT24C44 regardless of the "write enable latch" status. Figure 3. Read Cycle Timing SK CYCLE # SK VIH CE tPD 6 7 8 9 10 11 DI tPD DO HIGH-Z D0 D1 Dn tZ HIGH-Z Figure 4. Write Cycle Timing 1/FSK tSKH SK x tCES CE tDS DI tDH 1 tSKL 2 n tCEH tCDS Doc. No. 1083, Rev. R 6 (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 RECALL RCL/RECALL Data is transferred from the EEPROM data memory to RAM by either sending the RCL instruction or by pulling the RECALL input pin low. A recall operation must be performed before the EEPROM store, or RAM write operations can be executed. Either a hardware or software recall operation will set the "previous recall" latch internal to the CAT24C44. POWER-ON RECALL The CAT24C44 has a power-on recall function that transfers the EEPROM data to the RAM. After Powerup, all functions are inhibited for at least 200ns (Tpur) from stable Vcc. STORE STO/STORE Data in the RAM memory area is stored in the EEPROM memory either by sending the STO instruction or by pulling the STORE input pin low. As security against any inadvertent store operations, the following conditions must each be met before data can be transferred into nonvolatile storage: * The "previous recall" latch must be set (either a software or hardware recall operation). * The "write enable" latch must be set (WREN instruction issued). * STO instruction issued or STORE input low. During the store operation, all other CAT24C44 functions are inhibited. Upon completion of the store operation, the "write enable" latch is reset. The device also provides false store protection whenever VCC falls below a 3.5V level. If VCC falls below this level, the store operation is disabled and the "write enable" latch is reset. Figure 5. Recall Cycle Timing tRCC tRCP RECALL tRCZ DO HIGH-Z tORC tARC VALID DATA UNDEFINED DATA Figure 6. Hardware Store Cycle Timing tST tSTP STORE tSTZ DO HIGH-Z (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1083, Rev. R CAT24C44 Figure 7. Non-Data Operations CE 1 SK 2 3 4 5 6 7 8 DI 1 X X X X OP-CODE ORDERING INFORMATION Prefix CAT Device # 24C44 S Suffix I -TE13 Optional Company ID Product Number Temperature Range Blank = Commercial (0C to 70C) I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C) Tape & Reel Package P: PDIP S: SOIC, JEDEC L: PDIP (Lead-free, Halogen-free) V: SOIC, JEDEC (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) Notes: (1) The device used in the above example is a CAT24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Doc. No. 1083, Rev. R 8 (c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 04/17/2004 Revision Comments O Add Lead Free Logo Update Features Update Pin Configuration Update Block Diagram Update Instruction Set Update Device Operation Update Ordering Information Add Revision History Update Rev Number Update Pin Configuration Update Ordering Information Update Ordering Information Update Pin Configuration Update Reliability Characteristics Update Ordering Information 11/16/2004 04/17/2004 08/03/2005 P Q R Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM MiniPotTM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1083 R 08/03/05 |
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